![]() ![]() Replace clk below with - appropriate port name signal clk : std_logic constant clk_period : time := 10 ns BEGIN - Instantiate the Unit Under Test (UUT) uut : Decoder PORT MAP ( E => E, din => din, dout => dout ) - Clock process definitions clk_process : process begin clk <= '0' wait for clk_period / 2 clk <= '1' wait for clk_period / 2 end process - Stimulus process stim_proc : process begin - hold reset state for 100 ns. ALL ENTITY tb_Decoder IS END tb_Decoder ARCHITECTURE behavior OF tb_Decoder IS - Component Declaration for the Unit Under Test (UUT) COMPONENT Decoder PORT ( E : IN std_logic din : IN std_logic_vector ( 2 downto 0 ) dout : OUT std_logic_vector ( 7 downto 0 ) ) END COMPONENT -Inputs signal E : std_logic := '0' signal din : std_logic_vector ( 2 downto 0 ) := ( others => '0' ) -Outputs signal dout : std_logic_vector ( 7 downto 0 ) - No clocks detected in port list. ALL - Uncomment the following library declaration if using - arithmetic functions with Signed or Unsigned values USE ieee.numeric_std. ![]() 15 State-Machine Design Example Serial Parity Generator. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |